OpenFive is a solution-centric silicon company that is uniquely positioned to design processor agnostic SoC architectures with customizable and differentiated IP for artificial intelligence, edge computing, HPC, and networking solutions.OpenFiveoffers end-to-end expertise in architecture, design implementation, software, silicon validation and manufacturing to deliver high-quality silicon.
800G/400G Ethernet Solutions for Networking and Chiplets
past webinar
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Overview
Ethernet has been used as a mainstream solution for chip-to-chip and die-to-die connectivity. In this webinar, we will review some of the key required features of Ethernet MAC/PCS from 800G down to 10G. We will address various types of Forward Error Correction engines (FEC) to improve the BER of the channel/links. We will analyze how the latest advances in packaging technology have allowed moving the ethernet functions from the main die to chiplets simplifying the system and improving the cost/power/performance of the overall solution.
Key Learnings
Chip-to-Chip connectivity using Ethernet, improving link error rates and packaging technology
Target Audience
Designers, Architects, Marketing, Package engineers
Speakers
Ketan Mehta, Sr. Director, Product/Application Marketing, Interface IP
As the Sr. Director of Interface IP at OpenFive, Ketan Mehta is responsible for HBM Memory, Interlaken, Ethernet, Die-to-Die links, and other high-speed interfaces. With over 25 years of experience in engineering, product planning and marketing, Ketan has a rich background in IP connectivity solutions for various applications including high performance computing (HPC), AI, networking, data center, and storage. He received his M.S. degree in electrical engineering from The University of Texas at San Antonio, and his MBA from San Jose State University.
Moderator
Webinars Overview
Ethernet has been used as a mainstream solution for chip-to-chip and die-to-die connectivity. In this webinar, we will review some of the key required features of Ethernet MAC/PCS from 800G down to 10G. We will address various types of Forward Error Correction engines (FEC) to improve the BER of the channel/links. We will analyze how the latest advances in packaging technology have allowed moving the ethernet functions from the main die to chiplets simplifying the system and improving the cost/power/performance of the overall solution.
Key Learnings
Chip-to-Chip connectivity using Ethernet, improving link error rates and packaging technology
Who should attend?:
Designers, Architects, Marketing, Package engineers
Speakers
Ketan Mehta, Sr. Director, Product/Application Marketing, Interface IP
As the Sr. Director of Interface IP at OpenFive, Ketan Mehta is responsible for HBM Memory, Interlaken, Ethernet, Die-to-Die links, and other high-speed interfaces. With over 25 years of experience in engineering, product planning and marketing, Ketan has a rich background in IP connectivity solutions for various applications including high performance computing (HPC), AI, networking, data center, and storage. He received his M.S. degree in electrical engineering from The University of Texas at San Antonio, and his MBA from San Jose State University.
Moderator
REGISTER
This webinar is offered at three different times. Register for the time that works best for you.
Thursday, Mar 04
04:00 pm Pacific Standard Time
San Francisco
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Thursday, Mar 04
04:00 am Europian Standard Time
San Francisco1
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Thursday, Mar 04
04:00 am China Standard Time
Beijing