openfive

OpenFive is a solution-centric silicon company that is uniquely positioned to design processor agnostic SoC architectures with customizable and differentiated IP for artificial intelligence, edge computing, HPC, and networking solutions.OpenFiveoffers end-to-end expertise in architecture, design implementation, software, silicon validation and manufacturing to deliver high-quality silicon.

SiFive USB 3.2 IP Solutions Including Retimer for High-Speed Consumer Applications

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SiFive USB 3.2 IP Solutions Including Retimer for High-Speed Consumer Applications
SiFive USB 3.2 IP Solutions Including Retimer for High-Speed Consumer Applications

Overview

Join us in this webinar to learn more about our USB 3.2 IP solution, including Retimer, for high-speed consumer applications. We will review the IP engineering features, operations, configurations, protocols and implementation guidelines in detail.
SiFive’s USB 3.2 Gen2 Retimer IP cores are compliant with the USB 3.2 Appendix E standard. USB 3.2 Gen 2 supports up to 10 Gbps of bandwidth. It includes a USB 3.2 Gen2 single lane PCS layer and supports all low power states.

Key Learnings

  • Features of the USB 3.2 Gen2 IP cores
  • Implementation guidelines – integration and testing
  •  Market outlook, applications and other details

Target Audience

Consumer product chip designers, high-speed interface IP designers, IP application engineers, IP architects and system engineers.

Speakers

  • Vikas Aravind Kulkarni, Director, SoC IP Engineering, SiFive, Inc.
  • Sanket Apurvabhai Shah, Verification Lead, SiFive, Inc.
  • Ketan Mehta, Director, SoC IP Product Marketing, SiFive, Inc.

Moderator

Eric Esteve, Founder of IPnest and Analyst at SemiWiki

SiFive USB 3.2 IP Solutions Including Retimer for High-Speed Consumer Applications

Webinars Overview

Join us in this webinar to learn more about our USB 3.2 IP solution, including Retimer, for high-speed consumer applications. We will review the IP engineering features, operations, configurations, protocols and implementation guidelines in detail.
SiFive’s USB 3.2 Gen2 Retimer IP cores are compliant with the USB 3.2 Appendix E standard. USB 3.2 Gen 2 supports up to 10 Gbps of bandwidth. It includes a USB 3.2 Gen2 single lane PCS layer and supports all low power states.

Key Learnings

  • Features of the USB 3.2 Gen2 IP cores
  • Implementation guidelines – integration and testing
  •  Market outlook, applications and other details

Who should attend?:

Consumer product chip designers, high-speed interface IP designers, IP application engineers, IP architects and system engineers.

Speakers

  • Vikas Aravind Kulkarni, Director, SoC IP Engineering, SiFive, Inc.
  • Sanket Apurvabhai Shah, Verification Lead, SiFive, Inc.
  • Ketan Mehta, Director, SoC IP Product Marketing, SiFive, Inc.

Moderator

Eric Esteve, Founder of IPnest and Analyst at SemiWiki

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