SiFive HBM2/2E IP Subsystem – Features and Implementation Guidelines

Video Source


Join us for our next SiFive Connect webinar to learn more about the features of the HBM2/2E IP subsystem and how to implement the IP in an SoC. We’ll also address the market applications for HBM2/2E IP.
SiFive’s HBM2/2E IP subsystem solution is architected and designed to provide the highest performance and flexibility for integrating high bandwidth memory (HBM) directly into next-generation ASIC and 2.5D SoC system-in-package (SiP) solutions. It supports the HBM2/2E JEDEC specification for a multitude of foundry technology nodes.

Key Learnings

  • Features of the HBM2/2E IP subsystem
  • Implementation guidelines for 2.5D SoC SiP
  • Market applications and other details

Target Audience

AI chip designers, DRAM memory controller designers, high-speed interface IP designers, IP application engineers, IP architects and system engineers.


  • Ketan Mehta, Director, SoC IP Product Marketing, SiFive, Inc.
  • Pranav Kale, Staff Engineer, SoC IP Engineering, SiFive, Inc.
  • Ritam Das Adhikari, Manager, SoC IP Applications, SiFive, Inc


  • Michael Gianfagna, Analyst, SemiWiki