OpenFive

OpenFive is a solution-centric silicon company that is uniquely positioned to design processor agnostic SoC architectures with customizable and differentiated IP for artificial intelligence, edge computing, HPC, and networking solutions.OpenFiveoffers end-to-end expertise in architecture, design implementation, software, silicon validation and manufacturing to deliver high-quality silicon.

USB IP
Subsystem

Full range of USB controllers supporting USB 2.0 / USB 3.0 / USB 3.1 gen1 and gen2 in host and device mode of operation. Supports AXI interface and in-built DMA features.
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USB IP Subsystem

Key Features

SiFive provides a complete portfolio of USB-certified controllers with host and device functionality. They are integrated with our PHY partners in multiple foundries and nodes. FPGA boards are available for demo and prototype use.

USB IP Subsystem

USB IP Subsystem

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USB 3.1 Device Controller

USB 3.1 Device Controller

USB IP Subsystem

Details

  • Compliant with USB 3.1 Gen 2 specification, USB 3.1 PIPE interface
  • Supports 32/64 data bus width
  • AXI, AHB bus standards
  • Supports 32/64/128 bit data bus
  • Supports all USB 3.1 power down modes
  • Supports Ccontrol, bulk, Iiochronous and interrupt transactions
  • Bulk endpoint support streaming
  • Device can be configurable up to 15 IN and 15 OUT functional endpoints
  • Configurable number of function endpoints
  • Dynamically configurable endpoint FIFO for optimum usage of memory
  • Synchronous SRAM interface for FIFO
  • Fully integrated DMA controller

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USB 3.2 Retimer

USB 3.2 Retimer

USB IP Subsystem

High Level Features

  • Compliant to USB 3.1 Appendix E standard
  • Supports Gen 1(5G) and Gen 2(10G) speeds
  • Supports all low power states
  • Supports MCU CSR interface to drive ASIC control and status register
  • Supports PCS logic with 8b/10b for Gen1 and 128b/132b for Gen2 support
  • Supports SERDES interface
  • Optional support to external PHY with PIPE interface
  • SRIS architecture
  • “Pass through” and “local loopback” supported
  • Provision to monitor key events including internal errors
  • Provision to monitor link states
  • Option to tune PIPE control signal through CSR interface
  • Master loopback support for production test
  • Option to generate LFPS pattern in debug mode

IP Customization

If you already have a specific SoC IP spec in mind, our team can help you to customize the controller IP as per your requirements.

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