OpenFive is a solution-centric silicon company that is uniquely positioned to design processor agnostic SoC architectures with customizable and differentiated IP for artificial intelligence, edge computing, HPC, and networking solutions.OpenFiveoffers end-to-end expertise in architecture, design implementation, software, silicon validation and manufacturing to deliver high-quality silicon.
Senior Engineer I - Analog Design
Senior Engineer I - Analog Design
Responsibilities:
HBM2E SoC analog sub-block design such as DLL, PLL, HBMIO, Clktree, VCDL and DCC
Block-level architecture selection as per specs
Design and simulation across pvt to meet specs
Help in .lib generation and support review
Post-layout simulations
Help in Verilog code generation for block owned and validate with schematic
Signoff on collaterals
Requirements:
Minimum 3 years of experience in analog circuit design
Skilled at basics and device physics, with understanding of the following:
Current mirrors, bandgap reference, Opamp, common source amplifier smallsignal analysis and various topologies
Hands-on wrt of each block
Basics of design constraints, current mirror matching, Opamp types and circuitdesign, comparator circuit design, bgref circuit design, level shifter circuit design,GPIO driver, pre-driver full custom circuit design, Tx/Rx constraints understanding
Basic knowledge of the following layouts: antenna checks, antenna failure, latchupissues, ESD constraints and layout rules, ERC-related checks, matching, cross talk,coupling, shielding, guard ring usage, LEF generation, .lib characterization,extraction setup, drc lvs runs switch knowledge, IR drop requirements, EM issues,parasitic matching, parasitic reduction techniques, and static and dynamic IRanalysis
Completed at least one of the following circuit designs >1GHz speed: DLL fullcircuit design, PLL full chip circuit design, or LVDS/USB/DDR/HBM Full Chip circuitdesign