Senior Engineer I - ASIC Design
As a senior engineer RTL design, you will be working in SoC design, subsystem design. You will be responsible for microarchitecture of the and generate microarchitecture documents. You will be working with verification teams on achieving the area, power and performance goals. You will be supporting physical design teams, verification teams, software teams and FPGA teams to ensure we a high quality SoC subsystem to the customers and ensure successful tapeout.
- Micro architect SoC IP blocks & RTL implementation
- Will be responsible for RTL quality checks - Lint/CDC/LEC
- Generate appropriate documentation for hardware blocks.
- Responsible for analyse / debug / fixing issues reported by verification team
- Should be able to develop the synthesis constraints for the blocks / subsystem owned
- 4-7 years of experience with a Bachelors/ Masters degree in the field of Electrical, Electronics or computer engineering
- Experience with architecture and , micro-architecture of subsystems & blocks
- Expert level experience designing using Verilog, Good coding practices to create designs correct by construction
- Should have good knowledge of Interface IP blocks like PCIe or USB or Ethernet or DDRx controller, QSPI, DMA, or other similar blocks
- Should have good understanding of challenges / requirements associated with integrating multiple IP in a subsystem
- Good understanding power, performance requirements and how to achieve them
- Good understanding of verification flow
Should have designed one or more subsystem using PCIe or DDRx or USB or SATA….
- Familiarity with industry standard AMBA Bus protocols and products in the SoC IP space including AXI, APB is must
- Ability to learn quickly and willingness to proactively take on responsibilities beyond the job description to accomplish team goals
- Scripting : Perl/Bash/Csh/Python