OpenFive is a solution-centric silicon company that is uniquely positioned to design processor agnostic SoC architectures with customizable and differentiated IP for artificial intelligence, edge computing, HPC, and networking solutions.OpenFiveoffers end-to-end expertise in architecture, design implementation, software, silicon validation and manufacturing to deliver high-quality silicon.
Senior Staff Engineer I-VLSI

Senior Staff Engineer I-VLSI

OpenFive is looking for Senior Manager – RTL Design with strong RTL Design skills. 
The SOC IP Team is responsible for all in-house soft and hard IPs. As an employee, you will have the 
opportunity to work on any of the IPs in our portfolio which are as follows: 

  • 100G/400G Ethernet 
  • Memory Controllers and SoftPHYs
  • High Throughput/Low Latency Interlaken Controllers
  • D2D Controllers

We are a team with soft boundaries across teams and it is possible for you to work on one or more 
of these IPs from time to time. You would also get the opportunity to work on these IPs targeted for 
the latest tech nodes from different foundries Ex 5nm, 7nm etc. We also tapeout test-chips on a 
regular basis to prove our IPs in Silicon. This provides an excellent opportunity for you to learn the 
entire tapeout process and post-silicon validation as well. 


Our Team focuses on high-quality work and a strong work ethic! We have a very exciting workplace 
and look forward to having you on board. 

The job profile involves the following at a broad level and depending on the grade you are hired for 
you will get to work on various aspects of the job profile. 


Our workplace provides an excellent opportunity to enhance your skill set not only in RTL Design and 
Verification but an all-round perspective:

  • Understanding of the IP marketplace
  • View into the overall semiconductor industry trends 

Development of Industry Standard requirements and thus better Design/Verification ethics


  • Lead one or multiple IPs from the Architecture phase to final delivery. 
  • End-to-end execution of the IP
  • Prepare and manage schedules 
  • Day-to-day management of the team members who are part of this IP development. 
  • Deliver a high-quality IP
  • Interfacing with various internal teams including the AE teams
  • Managing customer expectations
  • You would also get the opportunity to interact directly with the customers at various points during the 
  • Some of these IPs are mixed-signal IPs and will need the candidate to have an adequate understanding of the various other domains, their requirements, and hand-off criteria. 



  • Micro-architected and designed large design
  • Very good understanding of verification methodology and be able to guide the verification team as per the design aspects
  • Capability to identify problem areas in design during Microarch stage itself
  • Capability to analyze designs from performance aspects 
  • Experienced at least one complete delivery from start to finish
  • Good analytical and Debug skills
  • Experience in leading teams and guiding them towards successful, high-quality, and timely execution. 
  • Good knowledge in at least one/two of these protocols: HBM or DDR, Ethernet, Interlaken, AMBA
  • Expected to have very deep knowledge/understanding of the blocks that you have worked on.  
  • You should also be towards a solution-oriented mindset. Only Positive Thinkers are welcome!
  • It would be an advantage if you have gone through one complete ASIC cycle
  • Worked on either FPGA-based validation or Emulation

Get in touch

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ASIC Design Specs

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