OpenFive is a solution-centric silicon company that is uniquely positioned to design processor agnostic SoC architectures with customizable and differentiated IP for artificial intelligence, edge computing, HPC, and networking solutions.OpenFiveoffers end-to-end expertise in architecture, design implementation, software, silicon validation and manufacturing to deliver high-quality silicon.
DFT Implementation lead

DFT Implementation lead

OpenFive is looking for a DFT Implementation Lead with strong DFT skills. The SOC IP Team is
responsible for all in-house soft and hard IPs. As an employee, you will have the opportunity to work
on any of the IPs in our portfolio which are as follows:

 

  • 100G/400G Ethernet
  • Memory Controllers and SoftPHYs
  • High Throughput/Low Latency Interlaken Controllers
  • D2D Controllers

 

We are a team with soft boundaries across teams and it is possible for you to work on one or more
of these IPs from time to time. You would also get the opportunity to work on these IPs targeted for
the latest tech nodes from different foundries Ex 5nm, 7nm etc. We also tapeout test-chips on a
regular basis to prove our IPs in Silicon. This provides an excellent opportunity for you to learn the
entire tapeout process and post-silicon validation as well.

 

We are looking for a DFT lead for our various high-speed interface IPs that we design in-house. These
IPs are on the bleeding edge with high-speed IOs (up to 20Gbps per IO) and some of these IPs like
HBM PHY and D2D PHY are completely embedded within the package i.e., they do not come out on
the package balls and utilize 2.5D packaging technology. For this kind of IPs, the DFT strategy is
completely different from what a regular SOC requires since it needs to target KGD binning. We are
looking for a DFT lead who can help us define and implement a comprehensive DFT strategy for
these IPs.


Requirements:

  • 6 -10 years of Experience in defining and implementing the DFT strategy for at least 2 hard IPs. For Ex. Serdes or DDR3/4/5 PHY.
  • Good in Verilog coding for synthesis and testbenches.
  • Experience in generating all the collaterals required for the customer who will be using these
  • IPs in their SOC, must understand IJTAG, SCAN, ATPG, JTAG, BSCAN concepts.
  • Ability to define the RTL requirements and DFT aware design lib elements required to make the design DFT compatible.
  • Test mode timing support, debug and closure.
  • Experience in ATE support and debug.

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