OpenFive is a solution-centric silicon company that is uniquely positioned to design processor agnostic SoC architectures with customizable and differentiated IP for artificial intelligence, edge computing, HPC, and networking solutions.OpenFiveoffers end-to-end expertise in architecture, design implementation, software, silicon validation and manufacturing to deliver high-quality silicon.
Senior Engineer I - VLSI

Senior Engineer I - VLSI

OpenFive, is looking for a Senior Engineer with strong  RTL Design skills. The SOC IP Team is responsible for all in-house soft and hard IPs. As an employee you will have the opportunity to work on any of the IPs in our portfolio which are as follows:


100G/400G Ethernet
Memory Controllers and Soft PHYs
High Throughput/Low Latency Interlaken Controllers
D2D Controllers

We are a team with soft boundaries across teams and it is possible for you to work on one or more of these IPs from time to time. You would also get the opportunity to work on these IPs targeted for the latest tech nodes from different foundries Ex 5nm, 7nm etc. We also tapeout test-chips on a regular basis to prove our IPs in Silicon. This provides an excellent opportunity for you to learn the entire tapeout process and post-silicon validation as well.
Our Team focuses on high-quality of work and strong work ethic! We have a very exciting workplace and look forward to having you on-board.
The job profile involves the following at broad level and depending on the grade you are hired for you will get to work on various aspects of the job profile.
Our workplace provides an excellent opportunity to enhance your skillset not only in RTL Design and Verification but an all-round perspective:
Understanding of the IP marketplace
View into the overall semiconductor industry trends
Development of Industry Standard requirements and thus better Design/Verification ethics



  • Will be given an independent block(s) in an IP to be owned end-to-end which includes Microarch development, RTL design, review of Verification plan and full debug support
  • Required to support Emulation activities as well
  • Will need to guide juniors technically.
  • Interface with customers on various deliverables




  • Candidate must have Worked on RTL design of major blocks
  • Worked on micro-arch of major blocks
  • Strong knowledge in Design (Verilog) and verification aspects of design
  • Experienced at least one complete delivery from start to finish
  • Good analytical and Debug skills
  • Capability to mentor Juniors in the team
  • Good knowledge in at least one/two of these protocols
  • HBM or DDR , Ethernet, Interlaken, AMBA
  • Expected to have very deep knowledge/understanding on the blocks that you have worked on


Soft-skills required:

  • Integrity
  • Curiosity
  • High-quality of work
  • Analytical skills
  • Good Communication skills

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ASIC Design Specs

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