OpenFive is a solution-centric silicon company that is uniquely positioned to design processor agnostic SoC architectures with customizable and differentiated IP for artificial intelligence, edge computing, HPC, and networking solutions.OpenFiveoffers end-to-end expertise in architecture, design implementation, software, silicon validation and manufacturing to deliver high-quality silicon.
Senior Engineer I - VLSI

Senior Engineer I - VLSI

  • Requierment
  • Experience in  deep sub-micron tech nodes (TSMC 6nm, 7nm, GF12, TSMC 12nm,....)
  • Complex high speed designs for edge computing applications  (3.2G HBM PHY, Processor hardening for PPA analysis)
  • Experience in Timing Closure/ECOs on block level and chip level in a highly complex clocking environments including clear understand of clock domain crossings, Should be able to work closely with Physical Design Teams
  • Good knowledge of Functional & DFT modes and constraints, Signal integrity, Good knowledge of de-rates (OCV, AOCV,POCV)
  • Will need to be hands-on, defining constraints, margins based on tech nodes, incorporating feedback from the Analog Team in the SDCs
  • Experience with EDA Tools and Methodologies for STA, STA based ECO, Synthesis - hierarchical synthesis, DFT handling, retiming, clock gating
  • Correlating results between STA and GLS with AMS
  • Understanding of power management and UPF concepts at Synthesis/PnR/STA domains
  • Good scripting skills; experience in Tempus is a plus
  • Experience in  deep sub-micron tech nodes (TSMC 6nm, 7nm, GF12, TSMC 12nm,....)
  • Complex high speed designs for edge computing applications  (3.2G HBM PHY, Processor hardening for PPA analysis)
  • Experience in Timing Closure/ECOs on block level and chip level in a highly complex clocking environments including clear understand of clock domain crossings, Should be able to work closely with Physical Design Teams
  • Good knowledge of Functional & DFT modes and constraints, Signal integrity, Good knowledge of de-rates (OCV, AOCV,POCV)
  • Will need to be hands-on, defining constraints, margins based on tech nodes, incorporating feedback from the Analog Team in the SDCs
  • Experience with EDA Tools and Methodologies for STA, STA based ECO, Synthesis - hierarchical synthesis, DFT handling, retiming, clock gating
  • Correlating results between STA and GLS with AMS
  • Understanding of power management and UPF concepts at Synthesis/PnR/STA domains
  • Good scripting skills; experience in Tempus is a plus

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