OpenFive is a solution-centric silicon company that is uniquely positioned to design processor agnostic SoC architectures with customizable and differentiated IP for artificial intelligence, edge computing, HPC, and networking solutions.OpenFiveoffers end-to-end expertise in architecture, design implementation, software, silicon validation and manufacturing to deliver high-quality silicon.
Senior Engineer II - VLSI

Senior Engineer II - VLSI

Open-Five transforms ideas into system-optimized ASIC solutions within the time-to-market parameters desired by customers. The company enhances the value of customers’ products by innovating at every stage of design – architecture, logic, physical, system, software, IP – and then continues to partner to deliver fully tested silicon and platforms. Open-Five applies an open business model that enables the company to uniquely choose best-in-industry IP, design methodologies, tools, software, packaging, manufacturing and test capabilities. The company has partnered with over 150 companies ranging from large semiconductor and systems manufacturers to high-profile start-ups, and has successfully completed tape-out of 300+ designs and shipped over 125 million ASICs to date.

Responsibilities:

  • Perform hands-on physical design and physical verification tasks across projects in advanced process nodes.
  • Own project specific ASIC development flow setup and maintenance.
  • Physical design tasks include floor-planning, place and route, CTS, timing closure, IR/EM analysis and LEC for block level and full chip flat/hierarchical designs. Co-ordinate full chip physical design and verification activities.
  • Physical verification tasks include creating setup and scripts for DRC, LVS, DFM, Antenna and density checks, report generation, analysis, debug and implementing fixes in the physical design database.
  • Ensure correct IP and pad-ring integration in block and flat designs.
  • Mentoring junior PD/PV team members and overseeing their tasks.

Requirements:

  • Personality - Team player, good written and verbal communication, quick learner
  • Education – B. Tech /M. Tech in Electronics Engineering
  • Experience – Minimum 5+ years
  • Skill set – Should have worked on advanced FinFET node designs.
  •  Experience with Cadence PnR/STA tools and Calibre, good scripting/automation skills is a must.

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