OpenFive is a solution-centric silicon company that is uniquely positioned to design processor agnostic SoC architectures with customizable and differentiated IP for artificial intelligence, edge computing, HPC, and networking solutions.OpenFiveoffers end-to-end expertise in architecture, design implementation, software, silicon validation and manufacturing to deliver high-quality silicon.
Senior Engineer I - DFT

Senior Engineer I - DFT

OpenFive is a solution-centric silicon company that is uniquely positioned to design processor agnostic SoC architectures with customizable and differentiated IP for artificial intelligence, edge computing, HPC, and networking solutions. OpenFive develops domain-specific SoC architecture based on high-performance, highly-efficient, optimized, differentiated silicon. OpenFive offers end-to-end expertise in architecture, design implementation, software, silicon validation and manufacturing for semiconductor companies and systems manufacturers.
 
Responsibilities:

  • Defining DFT Architecture or Spec at block and SoC level
  • Leading DFT activities by working with project stake holders to meet the goals
  • DFT Implementation in RTL/Netlist at block and SoC level as per specs for Memory BIST, Boundary Scan, Scan and IP test
  • Pattern generation and simulation in RTL, netlist at block and SoC level
  • Develop and validate DFT mode SDC constraints for Synthesis and STA
  • Project flow setup and execution
  • Post-layout simulations at block and SoC level
  • Verilog RTL coding and verification for test logic modules
  • Experience in planning and tracking DFT activities to closure
  • Mentoring and guiding team members on technical front

 
Requirements:

  • Minimum 5 years of experience in DFT
  • Experience in digital design and verification using Verilog, VHDL, SV
  • Expertise in SoC level DFT – Memory BIST & Repair, Boundary Scan, Scan Insertion, IP test strategy, IJTAG
  • Experience in handling high speed interface and mixed signal IPs for DFT
  • Experience in Mentor Tessent, Synopsys or Cadence DFT tool sets
  • Skilled in solving DFT design issues in RTL/Netlist and coverage improvements.
  • Skilled in ATE pattern delivery and silicon debug
  • Hands on in scripting using TCL, Unix shell, Perl
  • Strong communication and presentation skills
  • Focused and result oriented with eagerness to learn

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