OpenFive is a solution-centric silicon company that is uniquely positioned to design processor agnostic SoC architectures with customizable and differentiated IP for artificial intelligence, edge computing, HPC, and networking solutions.OpenFiveoffers end-to-end expertise in architecture, design implementation, software, silicon validation and manufacturing to deliver high-quality silicon.
Functional Lead - Verification

Functional Lead - Verification

OpenFive, is looking for Functional Lead with strong Design skills. The SOC IP Team is responsible for all in-house soft and hard IPs. As an employee you will have the opportunity to work on any of the IPs in our portfolio which are as follows:

  • 100G/400G Ethernet
  • Memory Controllers and Soft PHYs
  • High Throughput/Low Latency Interlaken Controllers
  • D2D Controllers

We are a team with soft boundaries across teams and it is possible for you to work on one or more of these IPs from time to time. You would also get the opportunity to work on these IPs targeted for the latest tech nodes from different foundries Ex 5nm, 7nm etc. We also tapeout test-chips on a regular basis to prove our IPs in Silicon. This provides an excellent opportunity for you to learn the entire tapeout process and post-silicon validation as well.

Our Team focuses on high-quality of work and strong work ethic! We have a very exciting workplace and look forward to having you on-board.

The job profile involves the following at broad level and depending on the grade you are hired for you will get to work on various aspects of the job profile.

Our workplace provides an excellent opportunity to enhance your skillset not only in RTL Design and Verification but an all-round perspective:

  1. Understanding of the IP marketplace
  2. View into the overall semiconductor industry trends
  3. Development of Industry Standard requirements and thus better Design/Verification ethics



  • May get to own one IP completely from end to end.
  • Will be required to Lead a team of engineers for delivering the IP
  • Define the IP test plan, coverage plan and TB architecture.
  • Design the various TB components along with other members in the team.
  • Will be required to be part of IP architecture discussions and contribute towards and efficient IP design.
  • Emulation support for the IP
  • Interface with customers for the assigned IPs for providing verification support



  • Minimum 8 years of experience in Verification
  • Very good knowledge of Verilog and UVM
  • Created the testplans for multiple blocks or IPs
  • Good verification discipline and aimed towards Zero-bug strategy.
  • Led at least 2 major blocks/IPs for complete verification.
  • Very good understanding of coverage fundamentals
  • Very good analytical and Debug skills
  • Mentored/led Juniors in the team.
  • Handled multiple projects in parallel.
  • Expected to have very deep knowledge/understanding on the blocks that you have worked on.
  • It would be an advantage if you have gone through one complete ASIC cycle.
  • Worked on either FPGA based validation or Emulation.
  • Good knowledge in at least one/two of protocols like HBM or DDR, Ethernet, Interlaken, AMBA

Get in touch

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ASIC Design Specs

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