OpenFive is a solution-centric silicon company that is uniquely positioned to design processor agnostic SoC architectures with customizable and differentiated IP for artificial intelligence, edge computing, HPC, and networking solutions.OpenFiveoffers end-to-end expertise in architecture, design implementation, software, silicon validation and manufacturing to deliver high-quality silicon.
Director - Analog and PHY IP Engineering

Director - Analog and PHY IP Engineering

OpenFive, is looking for PHY Director with strong Analog Design skills. The SOC IP Team is responsible for all in-house soft and hard IPs. As an employee you will have the opportunity to work on any of the IPs in our portfolio which are as follows:

100G/400G Ethernet
Memory Controllers and Soft PHYs
High Throughput/Low Latency Interlaken Controllers
D2D Controllers


We are a team with soft boundaries across teams and it is possible for you to work on one or more of these IPs from time to time. You would also get the opportunity to work on these IPs targeted for the latest tech nodes from different foundries Ex 5nm, 7nm etc. We also tapeout test-chips on a regular basis to prove our IPs in Silicon. This provides an excellent opportunity for you to learn the entire tapeout process and post-silicon validation as well.

Our Team focuses on high-quality of work and strong work ethic! We have a very exciting workplace and look forward to having you on-board.

The job profile involves the following at broad level and depending on the grade you are hired for you will get to work on various aspects of the job profile.

Our workplace provides an excellent opportunity to enhance your skillset not only in RTL Design and Verification but an all-round perspective:

Understanding of the IP marketplace
View into the overall semiconductor industry trends
Development of Industry Standard requirements and thus better Design/Verification ethics

 

Responsibilities:

  • Play a leadership role in managing the development of Interface and Analog IPs for internal ASIC or external customers
  •  Hands on experience of Hard analog or PHY blocks on circuit design in latest finfet nodes like 16nm and 7nm
  • Mentoring and leading the team in terms of BKM
  • Work with Sales, Marketing and PM teams across globe to drive the processes for solid IP Development methodology to ensure success with customers
  • Ability to support multiple customers and IP Deliveries
  • Strong knowledge in all aspects of integration of IP related to e.g. logic design and verification, physical design, packaging, test and characterization.

 

Requirements:

  • Minimum 15 years of experience in the IP Design and delivery of complex analog, mixed signal IPs or PHYs. Previous experience in DDR, HBM, SerDes is preferred.
  • Min Educational Qualifications: Master’s Degree or equivalent in Electronics and Computer Engineering. PhD Preferred.
  • Previous experience of leading large engineering teams is must
  • Expert knowledge of the complete ASIC and IP development life-cycle
  • Desire hands-on engineering experience involving a significant part of the ASIC/IP development flow
  • Excellent verbal and written communication and influencing/negotiation skills, including in direct customer and vendor engagements

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