OpenFive is a solution-centric silicon company that is uniquely positioned to design processor agnostic SoC architectures with customizable and differentiated IP for artificial intelligence, edge computing, HPC, and networking solutions.OpenFiveoffers end-to-end expertise in architecture, design implementation, software, silicon validation and manufacturing to deliver high-quality silicon.
Senior Engineer II - Layout Design

Senior Engineer II - Layout Design

OpenFive is a solution-centric silicon company that is uniquely positioned to design processor agnostic SoC architectures with customizable and differentiated IP for artificial intelligence, edge computing, HPC, and networking solutions. OpenFive develops domain specific SoC architecture based on high-performance, highly efficient, cost-efficient IP to deliver scalable, optimized, differentiated silicon. OpenFive offers end-to-end expertise in architecture, design implementation, software, silicon validation and manufacturing for semiconductor companies and systems manufacturers.

Analog Team works on variety of projects like high speed Memory interfaces, HBM3, high speed PLL (Ring & LC Based) ,DLL,TX,RX ,Serializer ,De serializer.

  • D2D PHYs working at more than 25 tbps (IO’s at 20gbps).
  • Exposure to 2.5 D technology like silicon interposer and INFO-OS.
  • Close working opportunity with local design team.
  • Opportunity to work on cutting edge technologies nodes like 3nm/5nm/7nm/12nm and multiple foundries like Samsung, TSMC, GF.

 

Responsibilities:

  • Responsible for Lead layout design and manage delivery of high frequency mixed signal blocks/IPs : DLL, PLL, HBMIO, Clktree, VCDL and DCC
  • Able to review sub blocks/blocks and provide technical inputs to the team.
  • Understand foundry, technology, layout specific issues and able to debug tool issues.
  • Signoff on collaterals.

 

Requirements:

  • Minimum 6 years of exp in Analog Layout.
  • Minimum education requirement is bachelor’s degree in Electrical Engineering.
  • Experience in handling blocks and macros layout towards successful, high-quality, and timely execution.
  • Experience with Cadence tools (Virtuoso) and Calibre verification tools like LVS, DRC, Extraction etc.
  • Excellent understanding of analog layout concepts and issues.
  • Experience with Finfet process and lower nodes like 3nm/5nm/7nm in TSMC foundry.
  • Understanding of low parasitic, high frequency design techniques.
  • Experience with multiple foundries in lower node.
  • SKILL scripting experience.
  • Excellent verbal and written communication.
  • Strong analytical and debug skills
  • Strong priority-resolution capabilities
  • Working well in a team environment is imperative in this role.

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