HBM2/2E IP Subsystem

The HBM2/2E IP is suitable for applications involving graphics, high-performance computing, high-end networking, and communications that require very high bandwidth, lower latency and more density.

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HBM2/2E IP SPECIFICATIONS

Key Features

Integrated HBM controller and HBM PHY subsystem solution supporting HBM2 and HBM2E JEDEC spec for a wide range of technology and foundry nodes. As an early advocate of 2.5D and 3D ASIC design technologies and by leveraging its experience from the industry’s first multiple successful 2.5D SoC SiP demonstration, SiFive plays a key role in enabling industry applications that leverage the HBM 3D-stacked DRAM technology.

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High Bandwidth Memory (HBM2/2E) – Product Brief

High Bandwidth Memory (HBM2/2E) – Product Brief

HBM2/2E IP Subsystem

HBM2/2E ASIC SiP (System in Package)

HBM2/2E ASIC SiP (System in Package)

Protocol controller

  • JEDEC (JESD235B) HBM2/2E DRAM specification compliant
  • Pseudo-channel mode support
  • Multi stack HBM2/2E memory support
  • Power down self-refresh modes
  • Low latency controller features
  • Per channel data rate – Up to 3.2Gbps/pin
  • Configurable independent channels
  • Memory access optimizations for bandwidth efficiency
  • DFI-like controller/PHY interface
  • Supports 1:1 & 2:1 PHY/controller frequency ratios
  • Memory die diagnostic features
  • JTAG connectivity for IEEE-1500 access, lane repair, training and loopback test modes
  • Multiple in-built test & diagnostic features

Die-to-Die Interposer I/O

  • CMOS I/O with programmable drive strengths
  • 3.2 Gbps / 1.6 GHz DDR with light output loading
  • Up to 5mm interposer trace length support meeting > 3.2 Gbps per pin date rate
  • Electrically compatible with JEDEC HBM2/2E spec
  • Optional differential receiver

PHY Layer

  • Ultra-low latency
  • Easily portable across technologies
  • Includes I/O, PLL & DLL
  • Coarse and fine grain I/O training
  • Low-power HBM memory and PHY modes
  • Complies to ESD requirements
  • Loopback support for testability
  • JEDEC (JESD235B) HBM2/2E DRAM specification compliant
  • Optional support for LLHBM
  • Process node supports – TSMC16/12nm, TSMC7nm, GF14/12nm, GF22FDx

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2.5D HBM ASIC SiP – Product Brief

2.5D HBM ASIC SiP – Product Brief

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Customization

If you already have a specific SoC IP spec in mind, our team can help you to customize controller IP as per your requirements.

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