Die-to-Die IP
Subsystem
in terms of low power, high throughput, and low latency links enabling faster time to integration for heterogenous chipset connections in wired communications, AI and HPC applications.
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D2D Controller IP (Die-to-Die Interface)
Die-to-Die (D2D) Controller IP is based on SiFive’s 8th generation of silicon-proven Interlaken IP core specifically for heterogenous chiplet solutions in wired communications, AI and HPC applications. With recent advances in package technologies it is possible to route high speed signals within a package connecting multiple die either on Interposer or on Organic Substrate. Die-to-Die Controller IP offers unique value proposition in terms of low power, high throughput and low latency links enabling faster time to integration.
Key Features
- Ultra-high-bandwidth and performance (For e.g. 1024-bit AXI interface at 2GHz can provide up to 2 Tbps)
- Ultra-low latency including Tx and Rx depending on the optional FEC module to improve BER
- Support for the SerDes rates up to 112 Gbps (CEI-112G-XSR) and aggregation support up to 48 lanes
- Independent SerDes lane enable/disable and fully programmable SerDes lane mapping
- Flexible AXI interface options including 64b, 128b, 256b, 512b and 1024b
- Optional In-band and Out-of-Band flow control
- Built-in error detection and interrupt structure
- Optional re-transmission module for error free transmission
- Configurable error injection mechanisms for testability
- Debug Features: PRBS generators/checkers and loopback support for both data and flow control
Downloads
D2D Controller IP Block Diagram
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Customization
If you already have a specific SoC IP spec in mind, our team can help you to customize the controller IP as per your requirements.
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