The demand for domain-specific silicon and workload-focused architecture is driven by several key factors. General-purpose processors used to be the workhorses for the majority of computing tasks. With transistor cost increasing, and the end of Dennard scaling, general-purpose processors have become very power-hungry and performance increases are hard to find from process technology alone – architecture plays a key role in workload acceleration. read more
Author: Dr. Shafy Eltoukhy, SVP & GM of OpenFive | Date: 08-16-2020
I recently had the opportunity to attend a SemiWiki webinar entitled “Chip-to-Chip Communication for Enterprise and Cloud”. The webinar was presented by SiFive and explored chip-to-chip communication strategies for a variety of applications. In the first part of the webinar, Ketan Mehta, director of SoC IP product marketing at SiFive explored the uses of the Interlaken protocol. This specification has been around since 2007.
I have been watching the trend for quite some time now that many advanced FinFET designs today are actually 2.5D systems in package. All of these 2.5D silicon interposer-based designs have high-bandwidth memory (HBM) stacks on board. Often there are multiple memory stacks in both 4-high and 8-high configurations. If you follow what’s been called the “more than Moore” revolution associated with 2.5 and 3D design. read more