Today, I am excited to announce the launch of OpenFive, a self-contained and autonomous custom silicon business unit of SiFive, Inc. OpenFive is solution-centric and uniquely positioned to design processor agnostic SoCs and deliver high-quality silicon.

The demand for domain-specific silicon and workload-focused architecture is driven by several key factors. General purpose processors used to be the workhorses for the majority of computing tasks. With transistor cost increasing, and the end of Dennard scaling, general
purpose processors have become very power hungry and performance increases are hard to find from process technology alone – architecture plays a key role in workload acceleration. We’re not alone in seeing this opportunity, as leading technology companies are embracing domain-specific accelerators targeted for applications such as AI training/inference, network virtualization and computational storage. Domain-specific or workload-focused silicon enable the cost-effective, scalable products desired by technology companies who want to own their
roadmap and vertically integrate their products with hardware and software IP. OpenFive is built around a balance of silicon expertise and customizable IP, including a focused portfolio of SoC IP to enable key design features. OpenFive’s advanced design methodologies enable the use of leading edge foundry nodes, including 5nm, with 2.5D packaging technology, to build Artificial Intelligence, Edge Computing, HPC, and Networking solutions. The OpenFive IP portfolio includes low-latency, high-throughput Interlaken connectivity fabric, 400/800G Ethernet, High-bandwidth memory (HBM2/E), USB subsystem IP, and die-to-die
interconnect IP for next-generation heterogeneous chiplet-style products. OpenFive’s broad industry expertise enables us to develop SoCs with a variety of processor cores, including RISC-V architecture as well as processors from Arm, Cadence, CEVA, and Synopsys.

This ISA-agnostic and open approach will help accelerate the adoption of RISC-V in new designs, as chip designers look for the best IP for each functional block inside their SoC designs. The open, free RISC-V ISA is the basis for the SiFive Core IP portfolio – the broadest in
the industry. SiFive cores, along with other RISC-V based cores, and cores from other ISA’s, can make a heterogeneous mix of application, embedded, and microcontrollers to enable a modern domain-specific design.

We’re incredibly excited about the opportunity that domain-specific silicon offers OpenFive customers in their next-generation products. With a heritage and expertise spanning more than 15 years, over 150M units shipped, and more than 350 tape-outs, OpenFive’s end-to-end
expertise in Architecture, Design Implementation, Software, Silicon Validation and Manufacturing enables the design and delivery of high-quality silicon, with first-time-right results.For more information on the portfolio of IP and silicon solutions OpenFive can provide for your new vertically-integrated, differentiated design project, please connect with us here. All trademarks referenced herein belong to their respective companies.

I have been watching the trend for quite some time now that many advanced FinFET designs today are actually 2.5D systems in package. All of these 2.5D silicon interposer-based designs have high-bandwidth memory (HBM) stacks on board. Often there are multiple memory stacks in both 4-high and 8-high configurations. If you follow what’s been called the “more than Moore” revolution associated with 2.5 and 3D design, you know that HBM memory stacks essentially paved the way for this revolution. The HBM memory specification is alive and well with new, high performance versions available today and more in the pipeline.

That’s why an upcoming webinar from SiFive caught my eye. Entitled SiFive HBM2/2E IP Subsystem: Features and Integration Guidelines, this webinar will take you through everything you need to know about the latest HBM standards and how to add HBM memory to your next chip. If you’re even considering the benefits of HBM memory stacks, you need to attend this webinar. The event will be hosted on Thursday, May 14, 2020 from 9AM-10AM and 6PM-7PM, Pacific Daylight Time. One of those time slots should work for you and you can register for the SiFive webinar here.

If you’re still on the fence about attending, here is some information that should help. The event will cover three aspects of HBM-based designs:

Ketan Mehta, Director, SoC IP Product Marketing at SiFive will cover markets, applications and roadmaps
Pranav Kale, Staff Engineer, SoC IP Engineering at SiFive will cover the features of the new HBM2/2E standards
Ritam Das Adhikari, Manager, SoC IP Applications at SiFive will cover implementation guidelines for these technologies
I will have the honor of moderating the event. I’ve reviewed the presentation material with the SiFive team and I can tell you it’s quite complete. You should have an honorary degree in HBM design after attending. Let’s look at a few details to whet your appetite.

First of all, what is HBM and why do you need it? HBM memory stacks are actually very dense memory subsystems implemented with 3D packaging technology. The latest version of the specification is HBM2E. SiFive prepared a useful table below that summarizes what the latest HBM2E spec can deliver when compared with more traditional memory technologies. I would pay particular attention to the density, power efficiency and bandwidth rows.

If your application needs ultra-dense, high-performance memory, HBM is really the only practical path forward. SiFive offers an HBM2/HBM2E IP subsystem that provides the critical elements of an Integrated HBM controller and HBM PHY that support both the HBM2 and HBM2E standards in multiple fab technologies. Below is a table summarizing the substantial technology and support offered by SiFive and their HBM2/2E subsystem. Note that CoWoS stands for chip-on-wafer-on-substrate, a 2.5D technology offered by TSMC.

The webinar goes on to cover popular applications for HBM technology, including high-performance computing, AI training/inference and networking. SiFive’s experience in these areas, as well as their technology roadmap are presented. You will also get a detailed overview of the extensive features and options supported by the SiFive HBM2/2E IP subsystem. The webinar concludes with an overview of implementation guidelines for your next HBM design. The following items are all addressed: Key implementation guidelines HBM2/2E bump map HBM2/2E PHY orientation in ASIC Loopback support for testability DFT methodology debug tools Collateral available Support infrastructure In short, everything you need to embark on an advanced 2.5D HBM-based design. There will also be a Q&A session with the presenters moderated by yours truly. As I’ve said, if you’re even thinking about HBM for your next design, you need to attend this webinar. You can register here. I hope to see you there.

I recently had the opportunity to attend a SemiWiki webinar entitled “Chip-to-Chip Communication for Enterprise and Cloud”.  The webinar was presented by SiFive and explored chip-to-chip communication strategies for a variety of applications.  In the first part of the webinar, Ketan Mehta, director of SoC IP product marketing at SiFive explored the uses of the Interlaken protocol. This specification has been around since 2007 and SiFive is on their 8^th generation of Interlaken IP. It is the protocol of choice for many demanding data communication applications.

Ketan began with an overview of the markets that can be served by Interlaken IP, which include networking, AI/ML, data center, high-performance computing/cloud. A wide range of markets that all share the need to move more and more data. Looking a bit closer at the problem, we see communication needs driven by massively parallel on-chip systems and chip-to-chip interfaces, the latter requirement is typically driven by the need to decompose a reticle-size chip into a series of smaller die for yield considerations. All these applications demand high performance, low latency data communication.

Ketan then introduced SiFive’s latest low-latency Interlaken IP. He went into quite a bit of detail about the capabilities of this new IP and discussed several real-world examples of where SiFive’s Interlaken IP is used in advanced applications. He concluded with an overview of SiFive’s Interlaken IP portfolio and a discussion of their roadmap.

Next, Sundeep Gupta, senior director of SoC IP at SiFive went into more details about the features and capabilities of SiFive’s Interlaken IP portfolio. As shown in the figure, below, SiFive Interlaken IP supports a broad range of Interlaken Alliance specifications. The IP is also available in two broad types, supporting high-bandwidth and low-latency.

Sundeep discussed in significant detail the key features of this IP portfolio, including performance, SerDes support, forward-error correction (FEC) support, user interface options and many more features. He then presented several block diagrams for various configurations, explaining the structure, data processing and data flow that can be implemented. What comes across during this part or the webinar is the flexibility of this IP portfolio.

Sundeep also went into details about how to create an optimal physical implementation of this IP during place and route. The ability to implement data redundancy was also covered, as well as information of how to use the IP in multi-core configurations, including lane distribution and lane remapping details.

Sundeep then discussed SiFive’s new low-latency IP for Interlaken support. This IP can deliver a 50% reduction in latency as compared with SiFive’s high-bandwidth IP. The features of this IP were covered, as well as an overview of how low-latency performance is achieved. He concluded his presentation with an overview of the deliverables provided by SiFive, summarized in the figure below.

The webinar concluded with a series of very detailed questions that further helped to illustrate the capabilities and roadmap of SiFive. If you’re involved in chip design requiring high-performance data communications, you will get a lot of benefit from this webinar. The good news is that a replay of the event is available here. The run time of the event is under 30 minutes, so you will learn a lot with a small investment in time.