openfive

OpenFive is a solution-centric silicon company that is uniquely positioned to design processor agnostic SoC architectures with customizable and differentiated IP for artificial intelligence, edge computing, HPC, and networking solutions.OpenFiveoffers end-to-end expertise in architecture, design implementation, software, silicon validation and manufacturing to deliver high-quality silicon.

Blogs

March 15, 2021
By Tom Simon, the Moderator at SemiWiki on 03-15-2021. AI vision processing moving to the edge is an undeniable industry trend. OpenFive, the custom silicon business unit of SiFive, discusses this trend with compelling facts in their recent paper titled “Enabling AI Vision at the Edge.” AI vision is being deployed in many applications, such as autonomous vehicles, smart cities, agriculture, industrial & warehouse robotics,

By Tom Simon, the Moderator at SemiWiki on 03-15-2021.

AI vision processing moving to the edge is an undeniable industry trend. OpenFive, the custom silicon business unit of SiFive, discusses this trend with compelling facts in their recent paper titled “Enabling AI Vision at the Edge.” AI vision is being deployed in many applications, such as autonomous vehicles, smart cities, agriculture, industrial & warehouse robotics, delivery drones, augmented reality, and smart retail & home.

Initially, it was only feasible to run AI vision processing in the cloud due to its capacity and processing power requirements. However, as billions of devices are deployed, processing solely in the cloud becomes unscalable. The network bandwidth requirements from billions of devices capturing high-resolution video from multiple cameras would exceed 5 petabytes per second!

On top of the logistical issues, cloud-based AI vision processing exacerbates privacy and latency issues. I for one would not want my self-driving car to rely on a wireless internet connection for making real-time driving decisions.

Associated with the push to move AI vision processing to the edge, there is large growth in the chipsets used to perform this processing. As shown in the chart, custom ASIC will become a dominant solution to provide the performance, power and functional advantage in AI Vision applications.

Enabling Edge AI Vision with RISC-V and a Silicon Platform

Edge AI Vision – Deep Learning Market

SiFive, OpenFive’s parent company, was founded on applying the ideas that have made software development so productive by eliminating the inefficiencies typically encountered. Yunsup Lee, co-founder and CTO of SiFive, participated in development of the RISC-V open- source instruction set architecture (ISA) in 2010. His vision has been to reduce the barriers for hardware design. The work of OpenFive is bearing fruit with impressive reductions in the cost, manpower and time needed to develop custom ASICs.

OpenFive’s use of SiFive’s RISC-V processor IP gives developers access to a well-developed set of operating systems, compilers, development packages and debugging tools. OpenFive’s AI vision platform is intended to speed up development of custom AI vision SoCs by providing multiple customizable subsystems that enable designers to focus on their key differentiators.

The platform contains just about every subsystem needed and can be tailored to eliminate unnecessary ones or to add specialized new blocks for specific applications. At the heart of the platform are SiFive’s multicore super-scalar Linux-capable U74 CPU complex, with support up to 8 cores and 2 MB of L2 cache. 32/64-bit LPDDRx with 6400MT/s provides gigabytes of high-bandwidth DRAMs required by edge AI applications. Powered by SiFive’s S21 embedded CPU, the platform management unit is responsible for power, boot and system health. The platform is secured by SiFive Shield that performs many security functions such as crypto, secure boot and key management. There is a vision subsystem with a vision DSP as well as MIPI interfaces. OpenFive includes an AI accelerator subsystem, of course, or users can add their own. Other customer specific accelerators can be added as well. The audio subsystem offers a wide range of features such as echo suppression and noise cancellation with its audio DSP. For visualization and graphics output, there is an integrated GPU. Naturally there is a wide range of high speed I/Os. There is even a die-2-die interface to improve performance with additional chiplets.

OpenFive’s business model allows their customers to engage with them during all stages of the ASIC development process. Customers can easily and quickly leverage OpenFive to complement their own skills, instead of needing to have in-house expertise in every one of the several dozen fields needed to produce a custom ASIC.

With open-source hardware and platform-based ASIC development, it is certain that we will see new products coming to market quickly that offer much hardware innovation. The rapid progress and growth that SiFive (and OpenFive) is experiencing are proof that there is pent-up demand for this. “Enabling AI Vision at the Edge” offers more details about OpenFive’s AI Vision platform. The paper is available for download on their website.

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January 18, 2021
Overview Demand for die-to-die and chip-to-chip interfaces has been growing steadily in the past few years due to new applications in cloud/data centers, AI (training and edge applications), and High-Performance Computing (HPC). The demand is driven by the requirements of high throughput, low latency and low power in these applications. Advances in packaging technology are further helping the adoption of heterogeneous systems with chiplets/known-good-die(KGD) assembly to create solutions that require the evolution

Overview

Demand for die-to-die and chip-to-chip interfaces has been growing steadily in the past few years due to new applications in cloud/data centers, AI (training and edge applications), and High-Performance Computing (HPC). The demand is driven by the requirements of high throughput, low latency and low power in these applications. Advances in packaging technology are further helping the adoption of heterogeneous systems with chiplets/known-good-die(KGD) assembly to create solutions that require the evolution of a new kind of interface popularly known as “Die-to-Die” interfaces.

Protocol and Interface Agnostic Universal D2D Controller for HPC and Chiplets

Figure 1 – D2D Interface Use Cases

Interface Types: Serial vs Parallel Approach

Driven by high-performance networking applications, SerDes has been the primary choice for connecting multiple chips and dies as switches and routers are at the forefront of the bandwidth requirements. For homogenous applications where multiple dies are on the same process nodes, USR/XSR SerDes are widely used to connect and scale the performance. However, this comes with a penalty of higher latency and power for each of the SerDes links as they are primarily PAM-4 based at 56G/112G speeds. The new trend is to connect dies using wider parallel IOs. These IOs are single-ended, similar to HBM and DDR memory technologies, and usually forward the clock to eliminate using power-hungry clock and data recovery circuits. With parallel IOs one can expect almost half the latency and power as compared to SerDes interfaces. There are many consortiums and standards working on parallel IOs such as OpenHBI, BoW, AIB, etc. OpenFive is a proponent of open interfaces and is actively involved in standardization efforts.

Packaging Choices: Interposer and Organic Substrate

Depending on the overall throughput requirements and the number of signals connecting the dies, one can use the interposer (various types) or organic substrate to stitch the dies together. Silicon interposers and other technologies allow more signal density, whereas organic substrates provide cost-effective packaging options. Organic substrate options are particularly attractive to chiplets with heterogenous dies (using different process nodes). There are many new advances in this area which we will cover in a future blog.

In this blog, we will talk about OpenFive’s recently launched D2D Controller. It sits on top of the D2D PHY (XSR SerDes/Parallel PHYs). The D2D Controller provides seamless connectivity to both types of interfaces.

D2D Controller

Protocol and Interface Agnostic Universal D2D Controller for HPC and Chiplets

Figure 2 – D2D Controller Block Diagram

The D2D Controller is essentially a link layer of the protocol stack. As compared to other protocols such as PCIe and Ethernet, this controller has the least overhead in terms of area and latency primarily with the intent to transfer data across two dies reliably in a few nanoseconds versus tens to hundreds of nanoseconds.

On the system side (left), the D2D Controller has Client Adaption Logic. This logic is configurable, and the customer can use either AXI-4, GMII, CXS, TileLink, or a native user interface, depending on the system’s needs. The AXI bridge supports master/slave interfaces with customer-defined widths and frequency.

The Protocol Layer takes care of end-to-end error-free delivery of the data. It has optional flow control to manage and back-pressure the traffic. This block also has optional re-transmission that stores user-defined packets based on the latency of the link.

Finally, the Framing Layer creates a seamless interface to industry-standard SerDes of various reach (LR, MR, VSR/XSR, etc.). The interface is also compile-time configurable to attach to upcoming parallel interfaces such as BoW, OpenHBI, and AIB. The framing layer also includes optional Forward Error Correction (FEC) blocks. Some of the lightweight FEC engines can improve the BER to below 1e-17.

Being configurable and agnostic to both the user interface and PHY interface is the key feature of this IP that allows SoC designers to not worry about the complex protocols.

For more information about OpenFive’s Protocol and Interface Agnostic D2D Controller, click on the following links:

  • Download our product brief HERE
  • View our widely popular webinar on Protocol Agnostic Die-to-Die Connectivity for Chiplet and HPC HERE
  • Read the press release on our Die-to-Die Interface Controllers for HPC and Chiplet Markets HERE
  • Learn more about the key features of our D2D Controller IP HERE

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October 11, 2020
OpenFive is hosting a webinar with CEVA on November 12th to talk about how OpenFive’s vision platform, leveraging CEVA vision and AI solutions. Which can get you to a differentiated solution for your product with as much or as little silicon participation on your part as you want. I talked briefly to Jeff VanWashenova (CEVA Sr. Dir of AI and Computer Vision) to get

OpenFive is hosting a webinar with CEVA on November 12th to talk about how OpenFive’s vision platform, leveraging CEVA vision and AI solutions. Which can get you to a differentiated solution for your product with as much or as little silicon participation on your part as you want. I talked briefly to Jeff VanWashenova (CEVA Sr. Dir of AI and Computer Vision) to get a sense of the opportunity. He sees a lot of interest from system product teams in automotive Tier1s and in other edge applications. These teams want to put differentiated high performance and low power AI at the heart of their edge products. But chip design isn’t their core skill. They need help, with vision, with AI and with a platform and silicon expertise to put the whole thing together.

OpenFive/CEVA partnership

That’s where the OpenFive and CEVA partnership comes in. CEVA and SiFive (the parent of OpenFive) already have an established partnership to bring AI to mainstream edge markets. CEVA is already well known in intelligent computer vision with their NeuPro architecture for CV, SLAM and wide-angle imaging applications. OpenFive adds to that the SiFive IP platform plus the silicon experience they bring with them in their previous incarnation as OpenSilicon, a full-service ASIC shop.

Between OpenFive and CEVA you have access to a turnkey design solution, all the way through manufacturing, assembly and test. While still being able to enjoy the advantage of RISC-V ISA extensions to optimize performance in the CPU core(s). Plus high performance and low power CV and neural net inferencing. You can develop and optimize your software to a platform customized to your specific needs and optimized for edge constraints.

About OpenFive

OpenFive is a solution-centric silicon company that is uniquely positioned to design processor agnostic SoC architectures. With customizable and differentiated IP for Artificial Intelligence, Edge Computing, HPC, and Networking solutions, OpenFive develops domain-specific SoC architectures based on high-performance, highly efficient, cost-optimized IP to deliver scalable, optimized, differentiated silicon. OpenFive offers end-to-end expertise in Architecture, Design Implementation, Software, Silicon Validation and Manufacturing to deliver high-quality silicon.

About CEVA

CEVA is the leading licensor of wireless connectivity and smart sensing technologies. We offer Digital Signal Processors, AI processors, wireless platforms and complementary software for sensor fusion, image enhancement, computer vision, voice input and artificial intelligence. All of which are key enabling technologies for a smarter, connected world. We partner with semiconductor companies and OEMs worldwide to create power-efficient, intelligent and connected devices for a range of end markets, including mobile, consumer, automotive, robotics, industrial and IoT.

CEVA ultra-low-power IPs include comprehensive DSP-based platforms for 5G baseband processing in mobile and infrastructure, advanced imaging and computer vision for any camera-enabled device and audio/voice/speech and ultra-low power always-on/sensing applications for multiple IoT markets. For sensor fusion, our Hillcrest Labs sensor processing technologies provide a broad range of sensor fusion software and IMU solutions for AR/VR, robotics, remote controls, and IoT. In artificial intelligence, we offer a family of AI processors capable of handling the complete gamut of neural network workloads, on-device. For wireless IoT, we offer the industry’s most widely adopted IPs for Bluetooth (low energy and dual mode), Wi-Fi 4/5/6 (802.11n/ac/ax) and NB-IoT.

August 16, 2020
Today, I am excited to announce the launch of OpenFive, a self-contained and autonomous custom silicon business unit of SiFive, Inc. OpenFive is solution-centric and uniquely positioned to design processor agnostic SoCs and deliver high-quality silicon. The demand for domain-specific silicon and workload-focused architecture is driven by several key factors. General purpose processors used to be the workhorses for the majority of computing tasks.

Today, I am excited to announce the launch of OpenFive, a self-contained and autonomous custom silicon business unit of SiFive, Inc. OpenFive is solution-centric and uniquely positioned to design processor agnostic SoCs and deliver high-quality silicon.

OpenFive’s Customizable Silicon-Focused Solutions

The demand for domain-specific silicon and workload-focused architecture is driven by several key factors. General purpose processors used to be the workhorses for the majority of computing tasks. With transistor cost increasing, and the end of Dennard scaling, general
purpose processors have become very power hungry and performance increases are hard to find from process technology alone – architecture plays a key role in workload acceleration. We’re not alone in seeing this opportunity, as leading technology companies are embracing domain-specific accelerators targeted for applications such as AI training/inference, network virtualization and computational storage. Domain-specific or workload-focused silicon enable the cost-effective, scalable products desired by technology companies who want to own their
roadmap and vertically integrate their products with hardware and software IP. OpenFive is built around a balance of silicon expertise and customizable IP, including a focused portfolio of SoC IP to enable key design features. OpenFive’s advanced design methodologies enable the use of leading edge foundry nodes, including 5nm, with 2.5D packaging technology, to build Artificial Intelligence, Edge Computing, HPC, and Networking solutions. The OpenFive IP portfolio includes low-latency, high-throughput Interlaken connectivity fabric, 400/800G Ethernet, High-bandwidth memory (HBM2/E), USB subsystem IP, and die-to-die
interconnect IP for next-generation heterogeneous chiplet-style products. OpenFive’s broad industry expertise enables us to develop SoCs with a variety of processor cores, including RISC-V architecture as well as processors from Arm, Cadence, CEVA, and Synopsys.

This ISA-agnostic and open approach will help accelerate the adoption of RISC-V in new designs, as chip designers look for the best IP for each functional block inside their SoC designs. The open, free RISC-V ISA is the basis for the SiFive Core IP portfolio – the broadest in
the industry. SiFive cores, along with other RISC-V based cores, and cores from other ISA’s, can make a heterogeneous mix of application, embedded, and microcontrollers to enable a modern domain-specific design.

We’re incredibly excited about the opportunity that domain-specific silicon offers OpenFive customers in their next-generation products. With a heritage and expertise spanning more than 15 years, over 150M units shipped, and more than 350 tape-outs, OpenFive’s end-to-end
expertise in Architecture, Design Implementation, Software, Silicon Validation and Manufacturing enables the design and delivery of high-quality silicon, with first-time-right results.For more information on the portfolio of IP and silicon solutions OpenFive can provide for your new vertically-integrated, differentiated design project, please connect with us here. All trademarks referenced herein belong to their respective companies.

May 4, 2020
I have been watching the trend for quite some time now that many advanced FinFET designs today are actually 2.5D systems in package. All of these 2.5D silicon interposer-based designs have high-bandwidth memory (HBM) stacks on board. Often there are multiple memory stacks in both 4-high and 8-high configurations. If you follow what’s been called the “more than Moore” revolution associated with 2.5 and

Webinar: Build Your Next HBM2/2E Chip with SiFive
I have been watching the trend for quite some time now that many advanced FinFET designs today are actually 2.5D systems in package. All of these 2.5D silicon interposer-based designs have high-bandwidth memory (HBM) stacks on board. Often there are multiple memory stacks in both 4-high and 8-high configurations. If you follow what’s been called the “more than Moore” revolution associated with 2.5 and 3D design, you know that HBM memory stacks essentially paved the way for this revolution. The HBM memory specification is alive and well with new, high performance versions available today and more in the pipeline.

That’s why an upcoming webinar from SiFive caught my eye. Entitled SiFive HBM2/2E IP Subsystem: Features and Integration Guidelines, this webinar will take you through everything you need to know about the latest HBM standards and how to add HBM memory to your next chip. If you’re even considering the benefits of HBM memory stacks, you need to attend this webinar. The event will be hosted on Thursday, May 14, 2020 from 9AM-10AM and 6PM-7PM, Pacific Daylight Time. One of those time slots should work for you and you can register for the SiFive webinar here.

If you’re still on the fence about attending, here is some information that should help. The event will cover three aspects of HBM-based designs:

Ketan Mehta, Director, SoC IP Product Marketing at SiFive will cover markets, applications and roadmaps
Pranav Kale, Staff Engineer, SoC IP Engineering at SiFive will cover the features of the new HBM2/2E standards
Ritam Das Adhikari, Manager, SoC IP Applications at SiFive will cover implementation guidelines for these technologies
I will have the honor of moderating the event. I’ve reviewed the presentation material with the SiFive team and I can tell you it’s quite complete. You should have an honorary degree in HBM design after attending. Let’s look at a few details to whet your appetite.

First of all, what is HBM and why do you need it? HBM memory stacks are actually very dense memory subsystems implemented with 3D packaging technology. The latest version of the specification is HBM2E. SiFive prepared a useful table below that summarizes what the latest HBM2E spec can deliver when compared with more traditional memory technologies. I would pay particular attention to the density, power efficiency and bandwidth rows.

Webinar: Build Your Next HBM2/2E Chip with SiFive

If your application needs ultra-dense, high-performance memory, HBM is really the only practical path forward. SiFive offers an HBM2/HBM2E IP subsystem that provides the critical elements of an Integrated HBM controller and HBM PHY that support both the HBM2 and HBM2E standards in multiple fab technologies. Below is a table summarizing the substantial technology and support offered by SiFive and their HBM2/2E subsystem. Note that CoWoS stands for chip-on-wafer-on-substrate, a 2.5D technology offered by TSMC.

The webinar goes on to cover popular applications for HBM technology, including high-performance computing, AI training/inference and networking. SiFive’s experience in these areas, as well as their technology roadmap are presented. You will also get a detailed overview of the extensive features and options supported by the SiFive HBM2/2E IP subsystem. The webinar concludes with an overview of implementation guidelines for your next HBM design. The following items are all addressed: Key implementation guidelines HBM2/2E bump map HBM2/2E PHY orientation in ASIC Loopback support for testability DFT methodology debug tools Collateral available Support infrastructure In short, everything you need to embark on an advanced 2.5D HBM-based design. There will also be a Q&A session with the presenters moderated by yours truly. As I’ve said, if you’re even thinking about HBM for your next design, you need to attend this webinar. You can register here. I hope to see you there.

April 1, 2020
I recently had the opportunity to attend a SemiWiki webinar entitled “Chip-to-Chip Communication for Enterprise and Cloud”.  The webinar was presented by SiFive and explored chip-to-chip communication strategies for a variety of applications.  In the first part of the webinar, Ketan Mehta, director of SoC IP product marketing at SiFive explored the uses of the Interlaken protocol. This specification has been around since 2007 and
Chip-to-Chip Communication for Enterprise and Cloud

I recently had the opportunity to attend a SemiWiki webinar entitled “Chip-to-Chip Communication for Enterprise and Cloud”.  The webinar was presented by SiFive and explored chip-to-chip communication strategies for a variety of applications.  In the first part of the webinar, Ketan Mehta, director of SoC IP product marketing at SiFive explored the uses of the Interlaken protocol. This specification has been around since 2007 and SiFive is on their 8th generation of Interlaken IP. It is the protocol of choice for many demanding data communication applications.

Ketan began with an overview of the markets that can be served by Interlaken IP, which include networking, AI/ML, data center, high-performance computing/cloud. A wide range of markets that all share the need to move more and more data. Looking a bit closer at the problem, we see communication needs driven by massively parallel on-chip systems and chip-to-chip interfaces, the latter requirement is typically driven by the need to decompose a reticle-size chip into a series of smaller die for yield considerations. All these applications demand high performance, low latency data communication.

Ketan then introduced SiFive’s latest low-latency Interlaken IP. He went into quite a bit of detail about the capabilities of this new IP and discussed several real-world examples of where SiFive’s Interlaken IP is used in advanced applications. He concluded with an overview of SiFive’s Interlaken IP portfolio and a discussion of their roadmap.

Next, Sundeep Gupta, senior director of SoC IP at SiFive went into more details about the features and capabilities of SiFive’s Interlaken IP portfolio. As shown in the figure, below, SiFive Interlaken IP supports a broad range of Interlaken Alliance specifications. The IP is also available in two broad types, supporting high-bandwidth and low-latency.

Chip-to-Chip Communication for Enterprise and Cloud

Sundeep discussed in significant detail the key features of this IP portfolio, including performance, SerDes support, forward-error correction (FEC) support, user interface options and many more features. He then presented several block diagrams for various configurations, explaining the structure, data processing and data flow that can be implemented. What comes across during this part or the webinar is the flexibility of this IP portfolio.

Sundeep also went into details about how to create an optimal physical implementation of this IP during place and route. The ability to implement data redundancy was also covered, as well as information of how to use the IP in multi-core configurations, including lane distribution and lane remapping details.

Sundeep then discussed SiFive’s new low-latency IP for Interlaken support. This IP can deliver a 50% reduction in latency as compared with SiFive’s high-bandwidth IP. The features of this IP were covered, as well as an overview of how low-latency performance is achieved. He concluded his presentation with an overview of the deliverables provided by SiFive, summarized in the figure below.

Chip-to-Chip Communication for Enterprise and Cloud

The webinar concluded with a series of very detailed questions that further helped to illustrate the capabilities and roadmap of SiFive. If you’re involved in chip design requiring high-performance data communications, you will get a lot of benefit from this webinar. The good news is that a replay of the event is available here. The run time of the event is under 30 minutes, so you will learn a lot with a small investment in time.

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