Chris Jones, Vice President, Products—September 16, 2021 Scalable High-Performance Computing SoC Design with RISC-V Whether you refer to the design concept as a disaggregated die, tiles, chiplets, or good ol’ multi-chip modules, a growing trend among SoC designers is making the interposer act like a ‘mainboard’ to host multiple chips. Together, these chips form a coherent whole product intended for a specific market and offer

By Tom Simon, the Moderator at SemiWiki on 03-15-2021. AI vision processing moving to the edge is an undeniable industry trend. OpenFive, the custom silicon business unit of SiFive, discusses this trend with compelling facts in their recent paper titled “Enabling AI Vision at the Edge.” AI vision is being deployed in many applications, such as autonomous vehicles, smart cities, agriculture, industrial & warehouse robotics, delivery

Overview Demand for die-to-die and chip-to-chip interfaces has been growing steadily in the past few years due to new applications in cloud/data centers, AI (training and edge applications), and High-Performance Computing (HPC). The demand is driven by the requirements of high throughput, low latency and low power in these applications. Advances in packaging technology are further helping the adoption of heterogeneous systems with chiplets/known-good-die(KGD) assembly to create solutions that require the evolution of

OpenFive is hosting a webinar with CEVA on November 12th to talk about how OpenFive’s vision platform, leveraging CEVA vision and AI solutions. Which can get you to a differentiated solution for your product with as much or as little silicon participation on your part as you want. I talked briefly to Jeff VanWashenova (CEVA Sr. Dir of AI and Computer Vision) to get a